FAQ

Questions

Questions - General matters

Q1.	How to ask the technical question about MD3306.

Q2.	How to receive any document, such as the data sheet.

Q3.	Can the board for evaluating MD3306 be purchased ?

Q4.	Can the Ethernet MAC module built in MD3306 be offered as IP for designing custom-ASIC ? Can the ATA module built in MD3306 be offered as IP for designing custom-ASIC ? In this case, is the semiconductor process which can use those IP limited to a specific maker's process?

Q5.	Please let me know the purchase root of MD3306.

Q6.	Please show the data about the thermal resistance of MD3306.

Questions - Hardware

Q1.	If CPU is one of the series of SH-3 or SH-4, is MD3306 connectable to it ?

Q2.	Teach me about the interruption function of MD3306.

Q3.	Is the whole chip reset if how much carries out time reset ?

Q4.	Teach me about the connection method of MD3306 and SH7751R.

Q5.	The phenomenon in which the data read from the internal register of MD3306 become unusual occurs.

Q6.	Can other devices use CS area where MD3306 was connected ?

Q7.	Teach me the terminal processing method of Ethernet and/or ATA channel which is not used.

Q8.	Although RAS, CAS, WEN, and DQM are directly linked between SH, MD3306 and SDRAMs directly, doesn't the signals of MD3306 and SH collide ?

Q9.	Although there are CASL/CASH/RASL/RASH in SH7709S, and there are CAS/RAS in MD3306, how do connect ?

Q10.	What are a descriptor ring and a buffer ? How are the data received from the outside carried to SDRAM in MD3306 ?

Q11.	Is SH with an external bus frequency of 120MHz connectable with MD3306 ?

Q12.	Although there are some terminals which do not have explanation in the terminal function of the data sheet, are these the terminals used for what ?

Q13.	Teach me the DMA operation of MD3306.

Q14.	Is it possible to connect two or more MD3306 to one SH4 ?

Questions - Ethernet function

Q1.	Can the Ethernet of two channels built in MD3306 operate independently, respectively ?

Q2.	How much is the performance of the Ethernet of MD3306 ?

Q3.	When carrying out the DMA transfer of the received data to external SDRAM, how many byte can it transmit at a time, and how much time does processing take ?

Q4.	What is the cause which an underflow generates in transmission ?

Q5.	What is the cause which "carrier undetecting" error generates ?

Q6.	Is there any auto negotiation function in Ethernet MAC of MD3306?

Q7.	Is there any auto negotiation function in Ethernet MAC of MD3306?

Q8.	Is it possible to transmit the read data through Ethernet simultaneously, reading data from HDD ?

Questions - ATA function

Q1.	Can ATA of two channels built in MD3306 operate independently, respectively ?

Q2.	How much is the performance of ATA of MD3306 ?

Q3.	Is it possible to connect ATA Compact Flash cards to the ATA port of MD3306?

Q4.	Teach me the notes on use of the built-in DMA controllers (ADMAC-1/2).

Q5.

When an ATA device stops data transfer in the middle of the data-in/out-burst of Ultra DMA, can the DMA transfer be resumed after that ?
Isn't the system in a deadlock state at this time ?
When an ATA device terminates data transfer in the middle of the data-in/out-burst of Ultra DMA, does it terminate normally?
Isn't the system in a deadlock state at this time ?

Q6.	Is it all right if "0" is preset to the fields of the read descriptor which are the object of the write-back operation by DMAC ? (In the case of Ethernet, "read descriptor" is "receiving descriptor".)

Q7.	Isn't the bit 26 of the read descriptor #0 (RD0) used? (In the case of Ethernet, "read descriptor #0" is "receiving descriptor #0".)

Q8.	Should the data length which wants to read by one ATA command issue be set as the RDR field ? For example, is "0200h" set to the RDR field in the case of set RBL=0200h, read 512 bytes by one ATA command issue, and read a total of 2 M bytes ?

Q9.	How much is the maximum amount of the data which can be written in HDD by one time of the ATA command using the DMA controller of MD3306 ?

Q10.	Is it necessary to repeat the ATA command (WRITE DMA) 256 times when writing 8 M bytes of data by DMA, and when the size of the data transmitted at once is 32 K bytes ?

Q11.	How to check the data transfer end by DMA at the time of WRITE DMA command ?

Answer

Answer - General Matters

Q1.	How to ask the technical question about MD3306.

A1	Please contact us.

Q2.	How to receive any document, such as the data sheet.

A2	You can download from the web Document download Page.

Q3.	Can the board for evaluating MD3306 be purchased ?

A3	Two kinds of boards, on which SH-3(SH7727) or SH-4(SH7750S) is mounted, can be purchased from the Hitachi ULSI systems. Those data are carried to our web.

Q4.	Can the Ethernet MAC module built in MD3306 be offered as IP for designing custom-ASIC ? Can the ATA module built in MD3306 be offered as IP for designing custom-ASIC ? In this case, is the semiconductor process which can use those IP limited to a specific maker's process?

A4	We offer the module of Ethernet MAC and ATA-5 as IP for designing custom-ASIC. They are not limited to a specific semiconductor process. Moreover, we also offer IP, such as PCI/PCI-X, wireless LAN, and gigabit Ethernet, etc.

Q5.	Please let me know the purchase root of MD3306.

A5	Renesas Electronics' semiconductor product selling company is dealing with the semiconductor products of Hitachi ULSI Systems. (former Hitachi's semiconductor product selling company)

Q6.	Please show the data about the thermal resistance of MD3306.

A6	The "reference value" of MD3306 thermal resistance is the following. However, the data shown below is not the value which Hitachi ULSI Systems guarantees. * junction-ambience (j-a): 34 deg-C/W Conditions : (1) No forced-air cooling (2) Tjmax = 125 deg-C

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Answer - Hardware

Q1.	If CPU is one of the series of SH-3 or SH-4, is MD3306 connectable to it ?

The bus interface of MD3306 is designed so that MD3306 can connect with many CPU of the SH-3/4 series. Hitachi ULSI systems has evaluated the system operation between MD3306 and the two kinds of SH-3/4 series (shown below) using above-mentioned MD3306 evaluation boards.
- SH-4: SH7750S (internal clock: 200MHz, bus clock: 100MHz)
- SH-3: SH7727 (internal clock: 133MHz, bus clock: 66MHz)
About other SH-3/4 series, Hitachi ULSI Systems has indicated the information about the clear portions (SDRAM connection etc.) of any functional difference which are clear at the data sheet (issuee by Hitachi Ltd. ) of each CPU in "MD3306 application note".

Q2.	Teach me about the interruption function of MD3306.

In MD3306, interruption, external interruption, and interruption to SH can be set up arbitrarily internal. (1) In case internal and/or external interruption of MD3306 are outputted to SH microcomputer, it can choose whether interruption without a priority which used IRL_N [3] (one terminal) or interruption with a priority which used IRL_N [3:0] (four terminals). -> setup of the bit 31 (INTOMODE bit) of IINTLVL register.
(2) Arbitrary interrupt levels can be set up to the interrupt request from EDAMC and /or ADMAC. -> isetup by the bit 15-0 of IINTLVL register, EDAC>1:2LVL[3:0], and ADAC>1:2LVL[3:0]. (3) It can choose whether using as four independent interrupt pins or using as priority encoded pins for EXINT_N [3:0] which is an external interruption input pins. In the case of the latter, an interrupt level can also be chosen. -> bit 31(EXIRQMD bit) of EXINTLVL1 register and EXINT_N [3:0] pins -> bit 27-0 of EXINTLVL1 register and bit 31-0 of EXINTLVL2 register in interrupt level in priority encoded interruption (Refer to "3.3.6 INTC/IOC register" of MD3306 a data sheet.)

Q3.	Is the whole chip reset if how much carries out time reset ?

The time in the case of carrying out soft reset of the whole chip is as follows. In this case, since ATA device is also reset, it depends for reset time on ATA-5 specification. (see MD3306 data-sheet 7.2.2.4) - Reset time ... 25 microseconds or more
- HDD access wait time after reset ... 2ms or more

Q4.	Teach me about the connection method of MD3306 and SH7751R.

In SH7751R, since the refreshment limitation in SH7751 is improved (based on the SH7751 data-sheet, second edition of Japanese version, issued by Hitachi Ltd.), the use restrictions about refreshment by SH7751 shown in MD3306 application note(clause 3.1) are not applied. Therefore, about refreshment of SH7751R, it becomes the same treatment as SH7750/SH7750S/SH7750R. However, since the terminal specifications of WE and DQM differ between SH7750 series and SH7751/SH7751R (SH7750 is a combination terminal and SH7751 is another terminal), to use SH7751R, the external circuit shown in MD3306 application note (clause 3.2) is required.

Q5.	The phenomenon in which the data read from the internal register of MD3306 become unusual occurs.

When the I/O area of MD3306 is set as the area for caching of SH microcomputer, since a cache will be carried out also to read/write access from/to the internal register of MD3306, the read data will not be not guaranteed.
Moreover, it becomes unusual also when an error is in a setup to BSC of SH microcomputer.

Q6.	Can other devices use CS area where MD3306 was connected ?

A6	In MD3306, it is the specification which occupies one area of CS space of SH-3/4. For this reason, other devices cannot use the area where MD3306 was connected.

Q7.	Teach me the terminal processing method of Ethernet and/or ATA channel which is not used.

A7	The rest terminals which attribute are "I" or "I/O" should carry out pull-up or pull down.

Q8.	Although RAS, CAS, WEN, and DQM are directly linked between SH, MD3306 and SDRAMs directly, doesn't the signals of MD3306 and SH collide ?

In MD3306, when not performing SDRAM access, MD3306 output signal becomes at high impedance. Moreover, since it performs after taking the right of bus from SH (in this case, the output signals of SH are at high impedance) when MD3306 accesses SDRAM, the signals of MD3306 and SH do not collide.
In addition, pull-up is required for the signals which serves as Hi-Z at the time of inactive.

Q9.	Although there are CASL/CASH/RASL/RASH in SH7709S, and there are CAS/RAS in MD3306, how do connect ?

MD3306 cannot access the SDRAMs distributing 32 MBytes of area of them at a time like SH7709S. RAS/CAS of MD3306 are connected to lower 32 Mbytes (RASL/CASL) side of the SDRAMs in the system which used SH7709S. However, in this case, the area which can be accessed from MD3306 to the SDRAMs is limited to llower 32 MBytes among the area of 64 MBytes.

Q10.	What are a descriptor ring and a buffer ? How are the data received from the outside carried to SDRAM in MD3306 ?

A10

In order to offload the software processing by CPU, four(4) DMA controllers of exclusive use are built in MD3306 for transmission and reception of the Ethernet frame, and the read/write of ATA data.
Hereafter, the case of Ethernet is taken for an example and they are explained.
By the data sheet of MD3306, the area of the external memory (SDRAM) which stores transmission or receiving frame of Ethernet is described as "buffer." and the pointer indicating the "buffer" is described as "descriptor". In many cases, two or more descriptors are set up to this "descriptor", respectively, in order to perform transmission and reception of two or more frames. When MD3306 refers to the descriptor, the top descriptor is referred to at the degree of the last descriptor ("1" is set to the last flag). Thus, since the descriptor has the ring structure, MD3306 data sheet has described the "descriptor ring".
The DMA controllers of MD3306 built-in performs DMA access of transmission/reception of any frame continuously, reading in an order from a top descriptor with interpreting its contents.
The data flow at the time of transmission and reception is as follows.
** data transmission **
Transmitting buffer -> Transmission FIFO in the DMA controller -> feLic
** data reception **
feLic -> Reception FIFO in the DMA controller -> Receiving buffer
(feLic: Ethernet MAC section)

Q11.	Is SH with an external bus frequency of 120MHz connectable with MD3306 ?

A11

No. The maximum bus frequency specification of MD3306 is 100MHz.

Q12.	Although there are some terminals which do not have explanation in the terminal function of the data sheet, are these the terminals used for what ?

A12

Terminals other than IRQOUT_N are using for the delivery inspection in our company. IRQOUT_N is an intact input terminal.

Q13.	Teach me the DMA operation of MD3306.

A13

DMA transfer operation of MD3306 is as follows,

1. Transmit or write operation (read data from SDRAM)
(1) System control software starts transmitting (or write) operation of MD3306.
(2) Descriptor fetch operation by MD3306
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) MD3306 fetches a descriptor
(a)-(c): 13 cycle
(d) MD3306 negates BREQ.
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 5 cycle
(3) DMA data transfer by MD3306
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) 32 bytes burst-read from SDRAM
(a)-(c): 17 cycle
(d) MD3306 negates BREQ
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 6 cycle
(g) Repeats above-mentioned from (a) to (f) operation until transmission data end.
(4) Descriptor write-back operation by MD3306
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) MD3306 write-back to descriptor
(a)-(c): 15 cycle
(d) MD3306 negates BREQ
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 2 cycle
(5) Repeats above-mentioned from (2) to (4) until descriptor end.

2. Receive or read operation (write data to SDRAM)
(1) System control software starts reception (or read) operation of MD3306.
(2) Descriptor fetch operation by MD3306
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) MD3306 fetches a descriptor
(a)-(c): 13 cycle
(d) MD3306 negates BREQ.
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 16 cycle
(3) DMA data transfer by MD3306
(After waiting until received data or read data can be prepared)
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) 32 bytes burst-write to SDRAM
(a)-(c): 16 cycle
(d) MD3306 negates BREQ
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 7 cycle
(h) Repeats above-mentioned from (a) to (g) operation until transmission data end.
(4) Descriptor write-back operation by MD3306
(a) MD3306 asserts BREQ to CPU.
(b) CPU asserts BACK to MD3306.
(c) MD3306 write-back to descriptor
(a)-(c): 9 cycle
(d) MD3306 negates BREQ
(e) CPU negates BACK.
(f) Internal processing of MD3306
(d)-(f): 2 cycle
(5) Repeats above-mentioned from (2) to (4) until descriptor end.

(Note)
1. The number of cycles in the above-mentioned sentence shows the number of cycles of the CPU bus.
example: 10 nsec/cycle at CPU bus 100MHz
2. The numbers of cycles shown in the above-mentioned sentence are the minimum value in each cases, and change the required number of cycles according to the condition of the system.

Q14.	Is it possible to connect two or more MD3306 to one SH4 ?

A14

Yes. Although it is possible, it is necessary to arbitrate the right of the CPU bus between SH-4 and MD3306 by using an external circuit, since MD3306 is premised on connecting with SH-4 and 1 to 1, BREQ/BACK has only 1 set.

Moreover, cautions are required also for the connection method of the interrupt-signal from MD3306 to SH-4.
(1) Input the interrupt-signal from each MD3306 into SH-4 separately.
or
(2) Input the interrupt-signal from MD3306(2) into SH-4 via the external-interrupt-pin of MD3306(1).

In addition, if Ethernet is used in three or more ports, there is also the method of using any multi-port Ethernet PHY.
(The same of the above is said of the case of SH-3.)

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Answer - Ethernet function

Q1.	Can the Ethernet of two channels built in MD3306 operate independently, respectively ?

A1	Yes. They operate independently.

Q2.	How much is the performance of the Ethernet of MD3306 ?

A2	The data is carried to our company web. However, the data shows the value of reference, since the performance of the Ethernet of MD3306 is sharply changed according to environment including OS or driver, etc. to be used of operation.

Q3.	When carrying out the DMA transfer of the received data to external SDRAM, how many byte can it transmit at a time, and how much time does processing take ?

If a DMA transfer is started, burst transmission of a 32-byte unit is performed in one cycle, and this DMA transfer will be repeated until it finishes transmitting all data. In burst transmission, 4 bytes of data are transmitted with one clock (BUSCLK).
Please refer to "6.1.3.4 DMA operation" of the MD3306 data sheet for details.

Q4.	What is the cause which an underflow generates in transmission ?

A4	As this cause, the latency time after performing the bus release demand to CPU is so long (in this case, other devices occupy the CPU bus), or a factor, like any error is in a setup to the register of EDMAC can be considered.

Q5.	What is the cause which "carrier undetecting" error generates ?

A5	When MD3306 is set as the half duplex mode and PHY is set as the full duplex mode (this means that the mode of MAC and PHY of operation is inharmonious), "carrier undetecting" error is reported in MD3306.

Q6.	Is there any auto negotiation function in Ethernet MAC of MD3306?

A6	No, MD3306 does not have the auto negotiation function. In a request of the auto negotiation function, please use PHY which is supporting it.

Q7.	Is there any auto negotiation function in Ethernet MAC of MD3306?

A7	No, MD3306 does not have the auto negotiation function. In a request of the auto negotiation function, please use PHY which is supporting it.

Q8.	Is it possible to transmit the read data through Ethernet simultaneously, reading data from HDD ?

Yes, it is possible. If you use the TCP/IP protocol, it is necessary to add the header/footer for constituting a TCP/IP packet. For this reason, software processing needs to perform TCP/IP processing to the data which read from HDD, and it is necessary to input into MD3306 the data which added required information as transmit data from Ethernet.

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Answer - ATA function

Q1.	Can ATA of two channels built in MD3306 operate independently, respectively ?

A1	Yes. They operate independently.

Q2.	How much is the performance of ATA of MD3306 ?

A2	The data is carried to our company web. However, the data shows the value of reference, since the performance of ATA of MD3306 is sharply changed according to environment including OS or driver, etc. to be used of operation.

Q3.	Is it possible to connect ATA Compact Flash cards to the ATA port of MD3306?

A3	If it is the Compact Flash card which is supporting the True IDE mode, it is connectable with the ATA controller.

Q4.	Teach me the notes on use of the built-in DMA controllers (ADMAC-1/2).

The DMA controllers for ATA (ADMAC-12) perform the DMA transfer of data to the address of the write-buffer (or from the read-buffer) described in the write descriptor (or read descriptor) currently prepared in external memory (SDRAM). Therefore, it is required to set beforehand to the internal register of MD3306 the information that the descriptor with which the address of the buffer is described exists in the external memory (SDRAM).
Write-descriptor is set up into CA1R3 or CA2R3 register. Read-descriptor is set up into CA1R4 or CA2R4 register. The address of the buffer is set up into each descriptor on the external memory. The address of write-buffer is set up into TBA field of the write-descriptor. The address of read-buffer is set up into RBA field of the read-descriptor. Here, the head address of write- and read-descriptor which set up into MD3306's internal registers hould be located into 16 bytes boundaries, respectively.
The head address of write- and read-buffer can be specified in the arbitrary byte addresses.

Q5.

When an ATA device stops data transfer in the middle of the data-in/out-burst of Ultra DMA, can the DMA transfer be resumed after that ?
Isn't the system in a deadlock state at this time ?
When an ATA device terminates data transfer in the middle of the data-in/out-burst of Ultra DMA, does it terminate normally? Isn't the system in a deadlock state at this time ?

Resumption is possible if it is the case where the ATA device pauses the DMA transfer according to the sequence specified by ATA specification (ATA-5). At this time, MD3306 or the ATA device resumes DMA automatically. Moreover, if it is the stop by the timing and the sequence which are specified to ATA specification, the ATA device is able to terminate the transmission normaly.
When it terminates by the specified sequence, the information which shows that the error occurred remains in the Error bit of ATA Status register. When an error occurs, the information which shows the error factor remains in ATA Error register. When the ATA device pauses or terminates the DMA transfer by the timing and the sequence which are not specified to the specification, the system may be in a deadlock state.
It is necessary to prepare the mechanism for performing the surveillance and release of a deadlock.

** Example **
The system control software supervises generating of a deadlock using a timer (for example, MD3306 internal timer MIATAx_WD_TIMER) etc. If the software detects a deadlock, the software can reset the system and will cancel the deadlock.

Q6.	Is it all right if "0" is preset to the fields of the read descriptor which are the object of the write-back operation by DMAC ? (In the case of Ethernet, "read descriptor" is "receiving descriptor".)

A6	The initial value of the fields which is write-backed by DMAC other than the RACT bit does not have especially specification. It is satisfactory even if it is "0".

Q7.	The initial value of the fields which is write-backed by DMAC other than the RACT bit does not have especially specification. It is satisfactory even if it is "0."

A7	Isn't the bit 26 of the read descriptor #0 (RD0) used? (In the case of Ethernet, "read descriptor #0" is "receiving descriptor #0" .)

Q8.	Should the data length which wants to read by one ATA command issue be set as the RDR field ? For example, is "0200h" set to the RDR field in the case of set RBL=0200h, read 512 bytes by one ATA command issue, and read a total of 2 M bytes ?

The data size to read from an ATA device by "one ATA READ DMA command" and "DMAC read DMA" is set to the RDR field.
When you read larger data than the size specified by the ATA command, like the example shown below, please repeat a series of processings of descriptor setting-ATA command issue-end processing by the required number of times by system control software. In MD3306, when reading 512 bytes by 1 time of the ATA command, the data length which can read by the DMA sequence of MD3306 is 512 bytes.

example 1:
When reading 512 bytes by one time of the ATA command and reading a total of 2 M bytes
[1] DMAC descriptor setup
(RACT=1, RBL=0200h (512), RDR=0200h (512))
[2] Set 01h to the ATA Secotor Count register, and issue the READ DMA command.
[3] DMA end processings (interrupting, status read etc.)
[4] Repeat the above-mentioned processing.
When only one descriptor is set up in above [1], repeats 4096 time the [1]-[3] operation.
When two or more descriptors are set up in above [1], repeats 4096 time the [2]-[3] operation.

example 2:
When reading 1024 bytes by one time of the ATA command and reading a total of 2 M bytes
[1] DMAC descriptor setup
(RACT=1, RBL=0400h (1024), RDR=0400h (1024))
[2] Set 02h to the ATA Secotor Count register, and issue the READ DMA command.
[3] DMA end processings (interrupting, status read etc.)
[4] Repeat the above-mentioned processing.
When only one descriptor is set up in above [1], repeats 2048 time the [1]-[3] operation.
When two or more descriptors are set up in above [1], repeats 2048 time the [2]-[3] operation.

Q9.	How much is the maximum amount of the data which can be written in HDD by one time of the ATA command using the DMA controller of MD3306 ?

A9	It is 63.5 K bytes (65536 - 512 bytes) when using the DMA controller of MD3306.

Q10.	Is it necessary to repeat the ATA command (WRITE DMA) 256 times when writing 8 M bytes of data by DMA, and when the size of the data transmitted at once is 32 K bytes ?

A10

Yes, it is.

Q11.	How to check the data transfer end by DMA at the time of WRITE DMA command ?

A11

MD3306 generates interrupt, whenever one processing of the WRITE DMA command (one descriptor) finishes. It can be checked that the WRITE DMA command has been completed (the DMA read from SDRAM of the data of the quantity specified by the descriptor was completed) by reading the information which write-backed to the descriptor, and/or the information on the interrupt status register of MD3306 by software processing at the time of interrupt generating.