Overview

MD3306 Series

Model No. PB-free or not Recommended Conditions on VPS Reflow Soldering MD3306BP not Pb-free Please refer to the clause of Recommended Conditions on VPS Reflow Soldering of the MD3306 Data Sheet. MD3306BPV Pb-free Please ask our company for the Recommended Conditions on VPS Reflow Soldering.

Important

Recommended Conditions on VPS Reflow Soldering differ by MD3306BP(not Pb-free) and MD3306BPV(Pb-free).

MD3306 is the peripheral LSI for SH-3/SH-4 which carried two 100/10 Mbps Ethernet MACs and two ATA-5 host interfaces, and it can realize application of high performance at the low cost which using Ethernet and storage devices.

MD3306 carries four highly efficient DMA controllers which built in the descriptor fetch and write-back function, and which connected to the external bus of SH-3 or SH-4 through the Synchronous DRAM (SDRAM) controller. Since MD3306 operates as a bus master, high-speed data transfer can be performed.

Feature

CPU Interface	Direct connectable to the externbal bus of SH-4 or SH-3. 100 MHz maximum operationg frequency of SH-3/4 32bit bus. Notifies interruption to SH by 15 interrupt levels or one interupt line (merging of the external interruption demand and MD3306 internal-interruption demand). Eight general I/O ports.
DMA Function	High-speed data transfer between Ethernet or ATA devices and the SDRAM on SH bus by the highly efficient DMA controller (EDMAC-1/2, ADMAC-1/2). Mitigates the load of software by the descriptor fech and write-back function. DMAC interrupts for 8 times of evey DMA transfers. Access to up to 64 MB of memory space is possible.
Ethernet Function	Two IEEE802.3.u compliant Ethernet MACs (feLic-1/2). 100/10 Mbps (full duplex operation). DMA transmission by buili-in DMAC (EDMAC-1/2). Tx FIFO 1k bytes and Rx FIFO 1k bytes in EDMAC-1/2.
ATA Function	Two ATA host interfaces (MIATA-1/2). Compliant to ATA/ATAPI-5 standard. Supports Ultra DMA (mode-2/4) and PIO (mode-0/4). Data transfer rate: 66MB/s (in Ultra DMA), 16MB/s (in PIO). DMA transmission by buili-in DMAC (ADMAC-1/2). Tx FIFO 512 bytes and Rx FIFO 512 bytes in ADMAC-1/2.

Appearance

Block Diagram

Specification

Item Specification CPU Interface Direct connectable to SH-4 MPX bus 100 MHz maximum operating frequency 32-bit width SDRAM Interface 100 MHz maximum operating frequency 32-bit width Maximum 64 Mbytes Ethernet Conforming to IEEE802.3 MACLayer Two(2) 100/10 Mbps MAC MII interface Descriptor fech/write-back function DMA Controller ATA Conforming to ANSI ATA/TAPI-5 host interface Two(2) host controller (Primary/Secondary, Master/Slave) Descriptor fech/write-back function DMA Controller Package PBGA 256pin Power supply 3.3V

MD3306 Evaluation Board (SH-4 edition)

MD3306 Evaluation Board (SH-3 edition)