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FAQ |
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Last Update: Jun. 12, 2003 |
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Questions
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Questions - General matters
Questions - CPU Interface
Questions - Low Speed Memory(I/O) Interface
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Answer
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| Q1. |
Teach me how to ask the technical question about MD3303. |
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| Q2. |
How to get any document, such as the data sheet. |
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A2
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You can download from our web. |
| Q3. |
Can the board for evaluating MD3303 be purchased ? |
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A3
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The board of the Compact PCI type which carried SH-4 (200MHz) can be purchased from the Hitachi ULSI systems. |
| Q4. |
Can the PCI module built in MD3303 be offered as IP for designing custom-ASIC ? |
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A4
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We offer the PCI module as IP, which 32/64 bit and 33/66 MHz are supported, for designing custom-ASIC. Mounting to FPGA/PLD is also possible.
Moreover, we also offer IP, such as SDRAM Controller, Ethernet, wireless LAN, and gigabit Ethernet, ATA, etc. |
| Q5. |
Please show the data about the thermal resistance of MD3303. |
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A5
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The "reference value" of MD3303 thermal resistance is the following. However, the data shown below is not the value which Hitachi ULSI Systems guarantees.
* junction-ambience (j-a): 21 deg-C/W
Conditions :
(1) No forced-air cooling
(2) Tjmax = 125 deg-C |
Answer - CPU Interface
| Q1. |
What is SH series which can connect MD3303 ? |
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A1
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MD3303 is connectable with SH7750/SH7750S/SH7750R which are Hitachi's SH-4 microcomputers. |
| Q2. |
Is MD3303 connectable with the external bus of what kind of SH-4 series ? |
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A2
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MD3303 supports the 32-bit MPX bus (the maximum clock frequency of 100MHz) of SH-4 series. The mounting model to the 100MHz bus, the connection method with the peripheral circuit, etc. are indicated by "MD3303 application note." |
| Q3. |
Is MD3303 connectable with SH-3 series ? |
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A3
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No. Since MD3303 supports only the MPX bus interface of SH-4, it is not connectable with SH-3 directly. In order to connect SH-3 and MD3303, it is necessary to add the logic which changes SH-3's external bus interface into MD3303's MPX bus interface. |
| Q4. |
Teach me the connection method of HCSRG, HCSPC, and HCSSD signal. |
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A4
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The use of HCSRG, HCSPC, and HCSSD signals is shown below.
HCSRG: CS signal for internal register space of MD3303
HCSPC: CS signal for PCI space
HCSSD: CS signal for SDRAM space connected to the SDRAM interface of MD3303
Please determine by your system specification whether the above-mentioned area will be assigned to the area of SH-4.
Although area #0-#6 can be used, generally area #0 (CS0 signal) is used as an object for program storing of SH-4. In this case, it is necessary to assign the three above-mentioned signals to the area of either area #1 (CS1) - #6 (CS6) in MPX mode. |
| Q5. |
Are the PALT registers used for what purpose ? |
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A5
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When accessing PCI space directly from SH-4, since the address outputted from SH-4 is only 26 bits, it cannot access the whole 32 bit-address space of PCI.
In order to solve this problem, in MD3303, the PALT registers are prepared for transrating 26 bits address of SH-4 into 32 bits PCI address.
The PALT registers are the tables of eight entries referred to when SH-4 accesses PCI space directly, and translates 26 bits address of SH-4 into 32 bits by setting desired data as the PALT registers beforehand. By using a PALT register, SH-4 can carry out direct access of 4 MBs PCI space per one entry of a PALT register. Since each table of eight entries is rewritable at any time, it can carry out direct access of SH-4 to 4GB of PCI space by setting up the PALT registers dynamically by the system control software.
Moreover, it is also possible by using the indirect-access registers (INDRCT_ADR, INDRCT_DATA, INDRCT_CMD) of MD3303 to carry out indirect access of the PCI space from SH-4. |
| Q6. |
Teach me the directions method in the case of carrying out memory access from SH-4 to PCI space. |
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A6
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The procedure changes with direct access or indirect access.
(1) In the case of direct access
According to the kind of access specified as the PCMDn (n=0 to 7) bit of PALT0-PALT7 registers corresponding to the PCI space to access, in case SH-4 access PCI space, a suitable command is sent out automatically.
(In the case of a memory cycle, "1" is set to PCMDn)
(2) In the case of indirect access
1) If the bit corresponding to the memory-read (Memory Read, Memory Read Line, or Memory Read Multiple) is set to the CMD bit of INDRCT_CMD register and "1" is simultaneously set to I/ORD bit, the cycle of the indirect memory-read to the address set to the INDRCT_ADR register will be performed, and read-data will be set to the INDRCT_DATA register.
2) If the bit corresponding to the memory-write (Memory Write, or Memory Write And Invalidate) is set to the CMD bit of NDRCT_CMD register and "1" is simultaneously set to I/OWT bit, the cycle for carrying out the indirect memory-write of the write-data set to the INDRCT_DATA register to the address set to the INDRCT_ADR register will be performed. |
| Q7. |
Which access is priority given when the built-in DMAC of MD3303 and SH-4 access simultaneously SDRAM connected to the SDRAM interface ? |
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A7
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Although priority is given to access from SH-4, change priority into other requester for 1 time to SDRAM of every access unit (max 32 bytes burst transfer). If SH-4 is accessing, priority will be changed into built-in DMAC, and priority will be changed into SH-4 if built-in DMAC is accessing. |
| Q8. |
While the built-in DMAC of MD3303 is performing data transfer between SDRAM and PCI bus, can SDRAM be accessed simultaneously also from SH-4 ?
Moreover, can access to the internal register and low-speed memory interface of MD3303 or PCI bus indirect access from SH-4 be performed at this time? |
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A8
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Yes. Those accesses are possible even if the MD3303 built-in DMAC is operating. |
| Q9. |
Is SH-4 whose external bus frequency is 120MHz connectable with MD3303 ? |
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A9
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No. The maximum bus frequency of MD3303 is 100MHz.
In addition, the CPU external bus clock inputted into the HCLK of MD3303 is used in the range of 33.3MHz to 100MHz. |
| Q1. |
Does MD3303 require 4 K bytes of I/O space of PCI space ? |
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A1
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Yes. MD3303 requires continuous 4k bytes of PCI I/O space.
In addition, depending on your system, the I/O space of PCI device may be restricted to 256 bytes or less. In case the host device performs a PCI configuration, the case where the host device cannot recognize the MD3303's demand about the PCI I/O space is also considered. In order to avoid this problem, it is necessary to correct the host's PCI driver so that the I/O space which is continuous 4 K bytes which MD3303 requires may be secured. |
| Q2. |
Teach me how to change the host mode and non-host mode of MD3303. |
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A2
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Connect the signals as follows.
(1) Host mode
When HBMD is set as "High", MD3303 will operate as host mode.
The state of the PCI interface signals related at this time becomes the following.
PIDSEL0-3 signal: Output
PREQ0-3 signal: Input
PGNT0-3 signal: Output
When connecting these signals with PCI bus, the PIDSEL/PREQ/PGNT signals corresponding to each PCI devices (maximum 4 devices) are connected.
(2) Non-host mode
When HBMD is set as "Low", MD3303 will operate as non-host mode.
Since the state of the PCI interface signal related at this time becomes the following, connects them with the signals by the side of the host bridge corresponding to them.
PIDSEL0-3 signal: Input
PREQ0-3 signal: Output
PGNT0-3 signal: Input
In non-host mode, since PIDSEL[3:1], PREQ[3:1] and PGNT[3:1] are not used, it carries out pull-up processing to them. |
| Q3. |
It is described by MD3303 data sheet at the time of host mode that the number of PCI devices which can connect with MD3303 is up to 4 devices. Are only up to two PCI cards connectable with MD3303, since a PCI edge connector is counted as 1 load ? |
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A3
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"up to 4 devices" means that four(4) pairs of REQ/GNT signals which can connect with PCI device's REQ/GNT are prepared for MD3303.
The relation with "number of PCI devices connectable with MD3303" and "load capacity of PCI bus" is shown in MD3303 data sheet. |
| Q4. |
Is which state of "0" and "1" of BE bit of INDRCT_CMD register effective ? |
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A4
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"0" is effective. The state where it was set up is outputted to PCI bus. |
| Q5. |
How long is the execution time of PCI indirect access in MD3303 ? |
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A5
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The execution time is influenced by the state of the PCI bus at that time. The running state of indirect access can be checked by monitoring the INDFLG bit of NDRCT_FLG register. |
| Q6. |
Teach me the setting method of the device number in the case of using INDRCT_ADDR register. |
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A6
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The device number at the time of configuration access is determined by the PCI device to which each of PIDSEL0-3 of MD3303 are connected. This relation is as follows.
PCI device connected to PIDSEL0: Device number = "0"
PCI device connected to PIDSEL1: Device number = "1"
PCI device connected to PIDSEL2: Device number = "2"
PCI device connected to PIDSEL3: Device number = "3" |
| Q7. |
Teach me how to connect MD3303 to the PCI bus of 5V system. |
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A7
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Since the PCI interface of MD3303 is 3.3V, it is not connectable with the PCI bus of 5V system directly. For this reason, in order to connect MD3303 with the PCI bus of 5V system, it is required to change into 5V the signal voltage of MD3303 which is 3.3V, or to change it into 5V-tolerant.
There are two kinds of methods of signal voltage conversion. A popular method is the signal voltage conversion which used the level shifter IC, such as SN74CBT series by TI, etc. In addition, there is also the method of using PCI-PCI bridge LSI which supported 5V interface. |
| Q1. |
Teach me how to connect HM5225165 (4Mx16-bitx4 SDRAM) to MD3303. |
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A1
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Connect as follows.
| Signal of MD3303 |
Signal of SDRAM |
| MBKADR1 |
BA1 |
| MBKADR0 |
BA0 |
| MADR12 |
A12 |
| MADR11 |
A11 |
| MADR10 |
A10 |
| MADR9 |
A9 |
| MADR8 |
A8 |
| MADR7 |
A7 |
| MADR6 |
A6 |
| MADR5 |
A5 |
| MADR4 |
A4 |
| MADR3 |
A3 |
| MADR2 |
A2 |
| MADR1 |
A1 |
| MADR0 |
A0 |
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Connection with other SDRAMs is shown in MD3303 application note. |
| Q2. |
Teach me the processing method of the MDP[3:0] terminals when not using parity. |
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A2
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MDP [3:0] terminals carrie out pull-up processing. Pull-up resistors recommend 4.7K ohm. Moreover, when not using parity, "0" is set as the bit-15 of MODE register. |
| Q3. |
Although inaccurate data may be written in SDRAM after DMA transfer completion, what is this cause ? |
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A3
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When the SDRAM used for DMA transfer with MD3303 is set as the object area of the cache of SH-4, data may be overwritten by write-back operation of the cache from SH-4 to the SDRAM area which the DMA transfer completed. |
| Q4. |
Although A0-A7 become effective as the column address in case the column address is outputted from SDRAM interface of MD3303 in case of 64Mbx16 SDRAM, are other signals (A8-A11) in what kind of state ? |
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A4
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When CAS is outputted, A8-A11 will be in "low" state. |
Answer - Low Speed Memory(I/O) Interface
| Q1. |
For what kind of case do use this interface ? |
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A1
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If the clock frequency of the external bus of SH-4 becomes close to 100MHz (muximum specification of MD3303), any other devices, such as ROM, SRAM, or slow I/O devices, cannot be connected to SH-4 external bus, since there is restriction of the load capacity specification of SH-4 external bus.
Since the data bus of low-speed device(s) is not connected direcytly with SH-4 external bus by making it go via MD3303, this interface can make the load capacity of SH-4 external bus mitigate. |
| Q2. |
Teach me the processing method of the terminals when not using this interface. |
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A2
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Carry out pull-up (recommendation resistance: 4.7k ohm) about intact pins (HCSMEM, HCSMSL, HLWE, HLOE, LCSLM, MDP). |
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HITACHI 
